FPGA Digital Timing System for Fusion Plasma Diagnostics in LHD
H.Nakanishi*, K.Kawahata, M.Kojima, M.Nonomura, M.Ohsuna, S.Imazu, S.Sudo, Y.Ito, Y.Nagayama (NIFS)
The digital timing system for LHD diagnostics was developed more than ten years ago as a VMEbus module which was operated by VxWorks RTOS. Through the fiber links, it can deliver the master trigger and the 10 MHz base clock which is modulated with the encoded trigger message. It has a simple tree structure from a master modulator to end demodulators whose output signal edges are all aligned to the delivered base clock. As the VME module and VxWorks were very costly to maintain, they have been ported into the new SoC platform, Xilinx Spartan-3E, that has 1.2 M programmable gates and Microblaze cpu which can run uClinux on it. Using its semi-finished commercial module Suzaku-S, the unit cost of a modulator box becomes one-eighth of previous VME one. In addition, it can output 6 delayed triggers, 6 divided clocks with their own (6) gating time, whereas VME provided 6-2-2. The same network communication schemes are completely implemented on uClinux, ported from the RPC source codes running on VxWorks. As such the semi-finished SoC platform is very useful to homemade an intelligent digitizer unit, another fast latching scaler module is now designed to be made for LHD.
This work is performed with the support and under the auspices of the NIFS Collaborative Research Program NIFS09ULHH503.