There is the 4 output beam line at the MainRing(MR) in J-PARC. The Accelerator protection system (MPS-MR) watches the devices which deals with destination of the beam.Then, the heart for the logic judgment carries out the complicated logic treatment using FPGA (Virtex-4 FX). This FPGA takes in destination information of the beam, and the logical operation with trouble information is carried out to make an output. Then, the FPGA takes in the information on the destination of the beam using the LAN. In addition, information of the abnormal equipment which becomes the reason for the beam to be stopped is sent to OPI using the LAN. By giving PowerPC core to realize this communication function in the FPGA, LINUX+EPICS is operated on the PowerPC core. Though there are both logic processing unit and CPU on one element, because, the information transfer in high speed between logic processing unit and CPU is possible without requiring the complicated external wiring. In this reason, the system can be very efficiently constructed. This paper describes the detail of the design and the implementation, as well as the experiences of the system in the operation of the J-PARC MR.