J-PARC Timing System is defined two kinds of timing, scheduled timing and synchronization timing. The scheduled timing is defined by a delay determined in advance from the reference trigger sent from the central timing control. Most devices and power supplies run with the scheduled timing. The scheduled timing system is configured one transmitter module in central control room and many receiver modules in device installed rooms (in total more than one hundred modules). Three signals which are the master clock, the reference trigger clock and the type, and LUT (Look-up Table) are distributed to the all receiver modules from transmitter module. An LUT is delay data block which is 256 * 8 array (The "256" is the number of "type", the "8" is the number of "trigger fan-out" per one receiver module). Then, a great number of "delay data" have to be managed for accelerator operation. The paper presents about the database to manage the timing delay for Linac and RCS*.