A timing system is a crucial subsystem of every accelerator, responsible for orchestrating the entire machine cycle by cycle. The current SNS timing system is based on the modified BNL solution which in turn is based on previous systems at other sites. The timing master is a collection of low functionality VME building blocks that are highly dependent on creative software to achieve the needed system functionality. The implementation technology of the whole system is backdated, making it impossible to build and maintain spares and boards for machine upgrades. At SNS we chose a roadmap which would allow a gradual upgrade of the timing system without having to redesign everything at once and yet provide a path for future modernization of the infrastructure. This paper presents progress on new timing master and receiver card, which will provide us with more flexible control and greater reliability by tremendously reducing the component count while still retaining compatibility with existing timing receiver units. The designs emphasize the use of FPGA technology in a way that simplifies the supporting software. The design of the system is a collaboration effort of ORNL and Cosylab.